1. The Field of the Invention
The present invention relates to semiconductor devices and methods for their construction. More particularly, the present invention generally relates to forming a local interconnect between adjacent transistors of a semiconductor device. More specifically, the present invention relates to processes for forming a local interconnect that provides an electrical connection between polysilicon gate electrodes of adjacent N-type and P-type transistors in a CMOS device. The invention also relates to semiconductor devices formed by employing such local interconnect processes.
2. The Background Art
Low resistance, shallow junction formation is one of the major challenges for scaling of MOS devices to submicron dimensions. Silicide layers are conventionally formed over source, drain, and gate regions to form low resistance contacts. The silicide is typically formed over the source or drain regions on the single crystal silicon substrate or on the polysilicon gate by reacting the silicon with a refractory metal such as titanium, cobalt, nickel and tungsten. In a typical commercial process, the silicide is formed after the source and drain regions have been implanted and annealed.
A number of different methods exist to implement the SALICIDE process. A conventional process is illustrated in FIGS. 1, 2, 3 and 4. FIG. 1 is a cross sectional view of a partially fabricated transistor after up to the spacer etching. The partially fabricated device includes polysilicon gate electrode 8 and gate oxide 4 which are straddled by spacers 6a and 6b on silicon substrate 2. Implanted P-type or N-type source and drain xe2x80x9ctip regionxe2x80x9d diffusions 7 and 9 have also been formed. In some processes these are referred to as xe2x80x9clightly doped drainxe2x80x9d regions.
FIG. 2 is a cross sectional view of a partially fabricated transistor after source and drain diffusion formation and ion implantation. P+or N+ion implantation may take place during the formation of source region 10 and drain region 12. In some situations source and drain regions will be formed in a single implant step. In many conventional fabrication schemes, well known to those skilled in the art, the source and drain regions are formed in a two step process, with implants being formed before and after spacer formation (as shown in FIGS. 1 and 2).
FIG. 3 is a cross sectional view of a partially fabricated transistor after dopant activation anneal. Typically, a high temperature annealing step is required to remove ion-implantation induced damage to the silicon substrate. During this high temperature annealing some limited diffusion of dopant through the silicon substrate 2 also occurs.
FIG. 4 is a cross sectional view of a partially fabricated transistor after silicidation. Silicide layers 14, 18 and 16 have been formed over source 10, polysilicon gate electrode 8 and drain 12 respectively. Thus, in typical conventional processes the silicide layer is formed after the source and drain regions have been implanted and annealed.
A number of problems with the conventional process have become increasingly critical with decreasing device size. Ion implantation induced damage of the silicon substrate requires high temperature annealing that causes dopant redistribution which significantly degrades the performance of smaller devices. More importantly, as device size decreases the thickness of the silicide layer must correspondingly decrease to preserve p-n junction integrity. Unfortunately, precise control of silicide layer thickness is often unattainable. Silicide layers must not grow beyond the edge of the source or drain region in the substrate. A silicide layer that grows beyond the edge of the source or drain region could become large enough to consume most or all of the source and drain regions thus destroying the p-n junction necessary for proper device functioning.
Silicide layer thickness has not been a significant problem in semiconductor fabrication until device sizes decreased below 0.25 xcexcm. For example, in a 0.18 xcexcm transistor (i.e., the channel region of an MOS transistor is 0.18 microns) the depth of the source and drain diffusions is only about 0.1 xcexcm. In such devices, the depth of the silicide layer must remain below about 300 xc3x85, a thickness that can be exceedingly difficult to reproducibly attain.
The Silicide as Diffusion Source (SADS) process offers a solution to the problems associated with the conventional process described above (F. C. Shone et al., Tech. Dig. IEDM, 407, 1985; R. Liu et al., Tech Dig. IEDM, 58, 1986; Q. F. Wang et al., IEEE Trans. Elec. Dev., 2486, 1992; J. Y. Tsai et al., MRS Symp., 245, 1995; C. Chu et al., Tech. Dig. IEDM, 245, 1990). In the SADS process, which is depicted in FIGS. 7A, 8A, 9A and 10A, silicide is formed on the source, drain, and polysilicon gate regions prior to formation of source and drain diffusions (See FIG. 8A). Then dopant atoms are implanted into the silicide at the locations where the source and drain diffusions are to be formed and the silicide located over the polysilicon gate electrode. (See FIG. 9A). After annealing, the dopant atoms residing in the silicide layers over the location of the incipient source and drain diffusions, diffuse into the silicon substrate to form source and drain diffusion regions (See FIG. 10A). Similarly, the dopant atoms residing in the silicide over the polysilicon gate electrode diffuse into the gate to form a doped polysilicon gate region (See FIG. 10A).
Formation of the source and drain diffusion after silicide formation ensures that the p-n junction is not consumed by the silicide layer since these diffusion regions grow away from the silicide layer. Furthermore, ion implantation directly into the silicide layer ensures that any resultant damage is largely confined within the silicide layer which is typically annealed at much lower temperatures than the silicon substrate. Therefore, dopant redistribution during annealing is not a significant problem when SADS process is used.
However, while the SADS process initially appeared promising, it has not become a viable commercial process because of at least one significant difficulty. In CMOS processes, N-type and P-type transistors are commonly coupled via a common gate input. Thus, adjacent N-type and P-type transistors typically share a polysilicon strip as their gate electrodes. As shown in FIG. 5 (top view of a partially fabricated CMOS structure) a common gate strip 5 is shared by an N-type transistor having source and drain diffusions 1a and 1b and a P-type transistor having source and drain diffusions 3a and 3b. In P-type devices, the gate electrode is typically doped with a P-type dopant such as boron. In N-type devices, the opposite is true; the gate electrode is doped with an N-type dopants such as phosphorus or arsenic.
The annealing step employed to form the source and drain regions in the SADS process also causes the N-type and P-type dopants in polysilicon gate strip 5 to laterally diffuse as shown. This is especially problematic because dopant atoms have relatively high diffusion coefficients in polysilicon. Therefore, during the annealing step N-type dopants rapidly diffuse into the PMOS gate electrode and P-type dopants rapidly diffuse into NMOS gate electrode. An N-type device with substantial concentrations of P-type dopants in its gate electrode cannot function properly. Similarly, a P-type device with substantial concentrations of N-type dopants in its gate electrode also cannot function properly. Therefore, the SADS process has not been found acceptable for commercial CMOS applications.
In any event it has become apparent that as device size shrinks improved methods for low resistance, shallow junctions are necessary. What is needed therefore is a process which solves the problem of dopant cross diffusion which occurs in polysilicon gates of CMOS devices when using the SADS process to form p-n junctions.
The present invention addresses this need by performing some or all annealing and diffusion steps while the two gate electrodes that are to be electrically connected are physically isolated from one another. Thus, the possibility of dopant cross diffusion across a common polysilicon strip is avoided. A local interconnection provides the necessary electrical connection between the two gate electrodes. The local interconnection is a conductive path formed at about the level of the polysilicon (i.e., below a first metallization layer and above a substrate) and between two adjacent gate electrodes. Some specific examples of local interconnections will be described below. In one case it is a tungsten plug formed in the space between an N-type polysilicon gate electrode and a P-type polysilicon gate electrode. In another case, a titanium nitride layer connects the N-type and P-type polysilicon gate electrodes.
One aspect of the invention provides a method for forming a CMOS structure having a first transistor coupled to a second transistor by a common gate contact on a partially fabricated electronic device. The method may be characterized as including the following sequence: (a) forming a first gate electrode on the first transistor and a second gate electrode on the second transistor; (b) providing dopant ions of a first conductivity to the first gate electrode and dopant ions of a second conductivity to the second gate electrode; and (c) forming a local interconnection electrically connecting the first gate electrode and the second gate electrode. As mentioned, the local interconnection is provided beneath a first metallization layer. In addition, it should retard diffusion of dopant atoms between the first and second gate electrodes during subsequent process steps.
Preferably, the first and second gate electrodes are formed as physically unconnected polysilicon structures by appropriately patterning a polysilicon layer, Typically, a step of annealing the CMOS structure is performed before forming the local interconnection. Because the two gate electrodes are physically unconnected during this anneal, dopant atoms will not diffuse between the first gate electrode and the second gate electrode.
In a preferred aspect of the invention, the above method is applied within a SADS process. In this aspect, the invention may be characterized as the following sequence: (a) patterning a polysilicon layer to provide a first gate electrode over a first transistor and a second gate electrode over a second transistor (preferably these gate electrodes are physically unconnected at this point); (b) forming a first silicide layer over first source and drain regions of the first transistor and a second silicide layer over second source and drain regions of the second transistor; (c) implanting dopant ions of a first conductivity into the first silicide layer and of a second conductivity into the second silicide layer; and (d) annealing to provide first source and drain diffusions that extend beyond the first silicide layer and second source and drain diffusions that extend beyond the second silicide layer without dopant ion diffusion between the first gate electrode and the second gate electrode; and (e) forming a local interconnection electrically connecting the first gate electrode and the second gate electrode.
As mentioned, SADS processes are particularly beneficial when forming devices of very small dimensions. Preferably, the source and drain diffusions are not more than about 0.1 xcexcm thick and the silicide layers are not more than about 30 nm thick.
Conventional materials may be employed in the processes of this invention. For example, the silicide layers preferably include at least one of CoSi2, TiSi2, NiSi2 and WSi2. The local interconnection may include titanium nitride, tungsten, aluminum, copper, titanium silicide, tungsten-nickel, titanium, nickel silicide or other suitable conductive material.
Yet another aspect of the invention provides a semiconductor device that may be characterized as including the following features: (a) a first transistor with a first gate electrode; (b) a second transistor with a second gate electrode; and (c) a local interconnection electrically coupling the first gate electrode to the second gate electrode. To be particularly useful, the first and second transistors should be of different types. For example, the first transistor may be an N-type transistor while the second transistor is a P-type transistor. Such N-type and P-type transistors coupled through their gate electrodes often form at least a portion of an inverter circuit.
Preferably, the CMOS structure will include thin silicide layers (e.g., not more than about 30 nm thick) over the source and drain diffusions of the two transistors. Thus, even with very thin source and drain diffusions (e.g., not more than about 0.1 xcexcm thick), source and drain diffusions will extend beyond the silicide layers. Such dimensions will typically be encountered in transistors having channel dimensions of less than about 0.2 xcexcm.
The local interconnects in the CMOS structures of this invention preferably have the structures described above with regard to the method aspects of this invention. It is also worth noting that the local interconnects are preferably formed on a trench type transistor isolation region between the first and second transistors.
These and other features and advantages of the invention will be described in more detail below with reference to the following drawings.